Phase-locked loop (PLL) circuits are widely used to synchronize clocks that are applied to circuit blocks. PLL circuits are used in a variety of modern electronic systems, including, for example communication systems, multimedia systems and in various other applications such as in FM demodulators, clock recovery circuits and tone decoders.
Conventional PLL circuits include a voltage-controlled oscillator (VCO). The operating characteristics of the VCO can have a significant impact on the performance of both the PLL and the system in which the PLL is used. In many applications, the performance of the PLL circuit may be improved if the VCO in the PLL has a relatively small gain, operates only in a particular frequency range and is relatively insensitive to noise from the power supply.
FIG. 1 is a graph of the frequency of the output signal of a VCO as a function of input voltage and operating conditions in a conventional PLL circuit.
As shown in FIG. 1, when a conventional VCO is designed to operate at a maximum operating frequency under the worst condition, the gain of the VCO may become relatively large when the VCO is operated in the best or typical conditions. This may cause the VCO to be sensitive to noise. Additionally, variation in the gain (Hz/Volt) of the VCO changes the loop bandwidth of the PLL circuit. As such, the operating characteristic of the PLL circuit may vary based on the operating condition and, under certain circumstances, the PLL circuit may not lock since the PLL circuit may operate in an unstable range. As is also apparent from FIG. 1, if the VCO is designed to satisfy a maximum operating frequency in a worst condition, the VCO may operate at an overly high frequency during a best condition.
When such a VCO is used in a PLL circuit, the operating speed of the divider and Phase/Frequency Detector (PFD) of the PLL circuit may be lower than the operating speed of the VCO. As a result, the PLL circuit may operate abnormally.